#!/bin/sh -e

if [ $# -ne 1 ]; then
    echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
    exit 1
fi

[ -f debian/patches/00patch-opts ] && . debian/patches/00patch-opts
patch_opts="${patch_opts:--f --no-backup-if-mismatch}"

case "$1" in
       -patch) patch $patch_opts -p1 < $0;;
       -unpatch) patch $patch_opts -p1 -R < $0;;
        *)
                echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
                exit 1;;
esac

exit 0

@DPATCH@
diff -Nur binutils-2.18.50.orig/gas/config/tc-mips.c binutils-2.18.50/gas/config/tc-mips.c
--- binutils-2.18.50.orig/gas/config/tc-mips.c	2008-07-11 03:05:29.000000000 +0800
+++ binutils-2.18.50/gas/config/tc-mips.c	2008-07-31 21:52:21.877261569 +0800
@@ -759,6 +759,9 @@
 /* ...likewise -mfix-vr4130.  */
 static int mips_fix_vr4130;
 
+/* True if -mfix-gs2f-kernel.  */
+static int mips_fix_gs2f_kernel;
+
 /* We don't relax branches by default, since this causes us to expand
    `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
    fail to compute the offset before expanding the macro to the most
@@ -3829,6 +3832,24 @@
 }
 
 /*
+ * Eliminate instruction fetch from outside 256M region.
+ * jr target pc &= 'hffff_ffff_cfff_ffff
+ * FOR KERNEL ONLY
+ */
+static void
+macro_build_jrpatch (expressionS *ex, unsigned int sreg)
+{
+  if (mips_fix_gs2f_kernel && sreg != 26 && sreg != 27 && sreg != AT) {
+    ex->X_op = O_constant;
+    ex->X_add_number = 0xcfff0000;
+    macro_build (ex, "lui", "t,u", AT, BFD_RELOC_HI16);
+    ex->X_add_number = 0xffff;
+    macro_build (ex, "ori", "t,r,i", AT, AT, BFD_RELOC_LO16);
+    macro_build (NULL, "and", "d,v,t", sreg, sreg, AT);	
+  } 
+}
+
+/*
  * Generate a "jalr" instruction with a relocation hint to the called
  * function.  This occurs in NewABI PIC code.
  */
@@ -3842,6 +3863,7 @@
       frag_grow (8);
       f = frag_more (0);
     }
+  macro_build_jrpatch (ep, PIC_CALL_REG);
   macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
   if (HAVE_NEWABI)
     fix_new_exp (frag_now, f - frag_now->fr_literal,
@@ -5987,6 +6009,26 @@
 	macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
       break;
 
+    case M_JR_S:
+	macro_build_jrpatch (&expr1, sreg);	
+        macro_build (NULL, "jr", "s", sreg);
+    	break;
+
+    case M_J_S:
+	macro_build_jrpatch (&expr1, sreg);	
+	macro_build (NULL, "j", "s", sreg);
+    	break; 
+
+    case M_JALR_S:
+	macro_build_jrpatch (&expr1, sreg);	
+	macro_build (NULL, "jalr", "s", sreg);
+    	break;
+
+    case M_JALR_DS:
+	macro_build_jrpatch (&expr1, sreg);	
+        macro_build (NULL, "jalr", "d,s", dreg, sreg);
+    	break;
+
     case M_J_A:
       /* The j instruction may not be used in PIC code, since it
 	 requires an absolute address.  We convert it to a b
@@ -6005,12 +6047,16 @@
       /* Fall through.  */
     case M_JAL_2:
       if (mips_pic == NO_PIC)
-	macro_build (NULL, "jalr", "d,s", dreg, sreg);
+ 	{
+ 	  macro_build_jrpatch (&expr1, sreg);	
+ 	  macro_build (NULL, "jalr", "d,s", dreg, sreg);
+ 	}
       else
 	{
 	  if (sreg != PIC_CALL_REG)
 	    as_warn (_("MIPS PIC call to register other than $25"));
 
+ 	  macro_build_jrpatch (&expr1, sreg);	
 	  macro_build (NULL, "jalr", "d,s", dreg, sreg);
 	  if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
 	    {
@@ -11130,9 +11176,11 @@
 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
   {"mfix-vr4130",    no_argument, NULL, OPTION_FIX_VR4130},
   {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
+#define OPTION_FIX_GS2F_KERNEL (OPTION_FIX_BASE + 6)
+  {"mfix-gs2f-kernel", no_argument, NULL, OPTION_FIX_GS2F_KERNEL},
 
   /* Miscellaneous options.  */
-#define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
+#define OPTION_MISC_BASE (OPTION_FIX_BASE + 7)
 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
   {"trap", no_argument, NULL, OPTION_TRAP},
   {"no-break", no_argument, NULL, OPTION_TRAP},
@@ -11428,6 +11476,10 @@
       mips_fix_vr4130 = 0;
       break;
 
+    case OPTION_FIX_GS2F_KERNEL:
+      mips_fix_gs2f_kernel = 1;
+      break;
+
     case OPTION_RELAX_BRANCH:
       mips_relax_branch = 1;
       break;
diff -Nur binutils-2.18.50.orig/include/opcode/mips.h binutils-2.18.50/include/opcode/mips.h
--- binutils-2.18.50.orig/include/opcode/mips.h	2008-06-13 05:44:53.000000000 +0800
+++ binutils-2.18.50/include/opcode/mips.h	2008-07-31 21:41:49.465260355 +0800
@@ -758,7 +758,11 @@
   M_DSUB_I,
   M_DSUBU_I,
   M_DSUBU_I_2,
+  M_JR_S,
+  M_J_S, /*JCX*/
   M_J_A,
+  M_JALR_S,
+  M_JALR_DS,
   M_JAL_1,
   M_JAL_2,
   M_JAL_A,
diff -Nur binutils-2.18.50.orig/opcodes/mips-opc.c binutils-2.18.50/opcodes/mips-opc.c
--- binutils-2.18.50.orig/opcodes/mips-opc.c	2008-07-08 03:11:15.000000000 +0800
+++ binutils-2.18.50/opcodes/mips-opc.c	2008-07-31 21:41:37.615362134 +0800
@@ -710,10 +710,12 @@
 {"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
 {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
+{"jr",      "s",	0,     (int) M_JR_S,	INSN_MACRO,		0,		I1	},
 {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	},
 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
    the same hazard barrier effect.  */
 {"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32	},
+{"j",       "s",	0,     (int) M_J_S,	INSN_MACRO,		0,		I1	}, /* jcx */
 {"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	}, /* jr */
 /* SVR4 PIC code requires special handling for j, so it must be a
    macro.  */
@@ -722,7 +724,9 @@
    assembler, but will never match user input (because the line above
    will match first).  */
 {"j",       "a",	0x08000000, 0xfc000000,	UBD,			0,		I1	},
+{"jalr",    "s",	0,     (int) M_JALR_S,	INSN_MACRO,		0,		I1	},
 {"jalr",    "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d,		0,		I1	},
+{"jalr",    "d,s",	0,     (int) M_JALR_DS,	INSN_MACRO,		0,		I1	},
 {"jalr",    "d,s",	0x00000009, 0xfc1f07ff,	UBD|RD_s|WR_d,		0,		I1	},
 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
    with the same hazard barrier effect.  */